1. Field of the Invention
Embodiments of the invention relate to a liquid crystal display, and more particularly, to a horizontal electric field liquid crystal display capable of preventing a reduction in the image quality caused by an inversion scheme.
2. Discussion of the Related Art
Liquid crystal displays (LCDs) generally display an image by adjusting a light transmittance of liquid crystals using an electric field. The liquid crystal displays are classified into a vertical electric field LCD and a horizontal electric field LCD depending on a direction of the electric field driving the liquid crystals. In the vertical electric field LCD, because a common electrode on an upper substrate and a pixel electrode on a lower substrate oppose each other, liquid crystals of a twisted nematic (TN) mode are driven due to a vertical electric field between the common electrode and the pixel electrode. The vertical electric field LCD has an advantage of a large aperture ratio but a defect of a small viewing angle. In the horizontal electric field LCD, liquid crystals of an in-plane switching (IPS) mode are driven due to a horizontal electric field between a pixel electrode and a common electrode that are positioned parallel to each other on a lower substrate. The horizontal electric field LCD has an advantage of a wide viewing angle.
The horizontal electric field LCD includes a liquid crystal display panel, on which the liquid crystals are arranged in a matrix format, and a driving circuit for driving the liquid crystal display panel. The driving circuit includes a data drive circuit generating a data voltage and a gate drive circuit generating a scan pulse.
The liquid crystal display panel, as shown in FIG. 1, includes a gate line GL and a data line DL crossing each other and a thin film transistor (TFT) that is positioned at a crossing of the gate line GL and the data line DL to drive a liquid crystal cell Clc. The TFT supplies a data voltage Vdata supplied through the data line DL to a pixel electrode Ep of the liquid crystal cell Clc in response to a scan pulse supplied through the gate line GL. For this, a gate electrode of the TFT is connected to the gate line GL, a source electrode of the TFT is connected to the data line DL, and a drain electrode of the TFT is connected to the pixel electrode Ep of the liquid crystal cell Clc. The liquid crystal cell Clc is charged to a voltage difference between the data voltage Vdata supplied to the pixel electrode Ep and a common voltage Vcom supplied to a common electrode Ec. An arrangement state of liquid crystal molecules changes due to an electric field produced by the voltage difference, and thus an amount of transmitted light is adjusted or the transmitted light is intercepted. The common electrode Ec is formed on the upper substrate or the lower substrate of the liquid crystal display panel depending on an applying manner of an electric field to the liquid crystal cell Clc. A storage capacitor Cst is formed between the common electrode Ec and the pixel electrode Ep of the liquid crystal cell Clc to keep a charging voltage of the liquid crystal cells Clc.
The horizontal electric field LCD, as shown in FIG. 2, is driven in an inversion scheme, in which a polarity of the data voltage Vdata is inverted every predetermined period based on the common voltage Vcom, so as to prevent deterioration and image sticking of the liquid crystal cell Clc. During an n-th frame period Fn, the liquid crystal cell Clc is charged to a positive data voltage Vdata(+) output by the data drive circuit and then is kept at a positive pixel voltage Vp(+) due to a parasitic capacitor Cgs (refer to FIG. 1), etc. of the TFT. A magnitude of the positive pixel voltage Vp(+) is a value obtained by subtracting an absolute value of a feed through voltage ΔVp from the positive data voltage Vdata(+). During an (n+1)-th frame period F(n+1), the liquid crystal cell Clc is charged to a negative data voltage Vdata(−) output by the data drive circuit and then is kept at a negative pixel voltage Vp(−) due to the parasitic capacitor Cgs, etc. of the TFT. A magnitude of the negative pixel voltage Vp(−) is a value obtained by adding an absolute value of a feed through voltage ΔVp to the negative data voltage Vdata(−). The feed through voltage ΔVp is defined by the following Equation 1.
                              Δ          ⁢                                          ⁢          Vp                =                                            Cgs              ′                                                      Cgs                ′                            +                              Clc                ′                            +                              Cst                ′                                              ⁢          Δ          ⁢                                          ⁢          Vg                                    [                  Equation          ⁢                                          ⁢          1                ]            
In the above Equation 1, Cgs′ indicates a parasitic capacitance of the parasitic capacitor Cgs between the gate electrode and the source electrode (or the drain electrode) of the TFT, Clc′ indicates an equivalent capacitance of the liquid crystal cell Clc, Cst′ indicates a capacitance of the storage capacitor Cst, and ΔVg indicates a difference voltage between a gate high voltage and a gate low voltage.
As indicated in Equation 1, even if positive and negative data voltages of the same scale level are respectively supplied to the liquid crystal cells Clc during two frame periods through the inversion scheme, a charge amount of the liquid crystal cells Clc during the frame period where the positive data voltage is supplied is less than a charge amount of the liquid crystal cells Clc during the frame period where the negative data voltage is supplied because of a difference between charging voltages of the parasitic capacitor Cgs during the frame periods. For example, while the parasitic capacitor Cgs is charged to a difference voltage 10V between a gate high voltage 25V and a positive white voltage 15V during the n-th frame, the parasitic capacitor Cgs is charged to a difference voltage 24V between the gate high voltage 25V and a negative white voltage 1V during the (n+1)-th frame. Therefore, a charge amount of the liquid crystal cells Clc during the frame period where the positive data voltage is supplied is less than a charge amount of the liquid crystal cells Clc during the frame period where the negative data voltage is supplied because of the feed through voltage ΔVp affected by a difference between the charging voltages of the parasitic capacitor Cgs during the frame periods. If the charge amount of the liquid crystal cell Clc varies every frame period, the deterioration in the image quality such as a flicker and image sticking occurs because of non-uniformity of data. The storage capacitor Cst is necessary and the capacitance Cst′ of the storage capacitor Cst has to be large so as to reduce the non-uniformity of the charge amounts of the liquid crystal cell during frame periods. However, in the related art horizontal electric field LCD, an aperture ratio is reduced because of the storage capacitor Cst.
Further, a method for controlling a level of the common voltage Vcom depending on a magnitude of a voltage offset resulting from the feed through voltage ΔVp has been proposed so as to solve the non-uniformity of the charge amounts of the liquid crystal cell Clc during frame periods. However, in the liquid crystal display, because the magnitude of the voltage offset resulting from the feed through voltage ΔVp varies every location, it is impossible to control an optimum common voltage at each location through only a change in the level of the common voltage Vcom being a constant voltage. Accordingly, it is limited to prevent the deterioration in the image quality caused by the non-uniformity of the charge amounts of the liquid crystal cell during the frame periods.